Turning to FIG. 1, an example of a conventional communication system 100 can be seen. As shown, this system generally comprises functional circuits 102-1 and 102-2 that communicate with one another over a communication channel (which generally includes codes 104-1 and 104-2, transceivers 106-1 and 106-2, and bus 108). When transmitting data across a bus 108, transitions between cycles can be costly in terms of power consumption, so the codecs 104-1 and 104-2 are employed to reduce current consumption associated with these transitions. For example, if it assumed that the bus 108 is 4 bits wide, an transition from “0000” to “1111” is much more costly than a transition from “0000” to “0001.” Thus, to avoid the costly transitions, codecs 104-1 and 104-2 employ what is known as “invert codes,” which introduces an extra bit to the bus 108 to indicate an inverse. For example, as shown in FIG. 1, bus 108 is 4 bits wide with an extra invert bit (effectively making the bus 108 5 bits wide). In this example, when there is a transition from “0000” to “1111,” the invert bit is toggled to “1” so that the bus transmits “10000.” By using the invert bit, it allows the number of transitions to be limited to 3 (instead of 4) with a 4-bit bus.
While this “invert code” system (i.e., system 100) can reduce the peak current by up to 50% and reduce energy consumption by up to 30%, there are some drawbacks. Namely, these systems are also less than optimal in savings related to peak current and energy consumption. Thus, there is a need for an improved system.
Some examples of conventional systems are: Davis et al., “Interconnect limits on gigascale integration (gsi) in the 21st century,” Proceedings of the IEEE, vol. 89, no. 3, pp. 305-324, 2001; Caignet et al., “The challenge of signal integrity in deep-submicrometer CMOS technology,” Proceedings of the IEEE, vol. 89, no. 4, pp. 556-573, 2001; Agarwal et al., “Modeling and analysis of crosstalk noise in coupled rlc interconnects,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 5, pp. 892-901, 2006; Tang et al., “Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections,” INTEGRATION, the VLSI journal, vol. 29, no. 2, pp. 131-165, 2000; Sotiriadis et al., “Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies,” Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design. IEEE Press, 2000, pp. 322-328; Stan et al., “Bus-invert coding for low-power I/O,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 3, no. 1, pp. 49-58, 1995; U.S. Pat. No. 6,834,335; and U.S. Pat. No. 7,640,444.